The present invention relates to the manufacture of integrated circuits (ICs), and more specifically, to the incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield.
Integrated circuits are typically fabricated by optical lithographic techniques. Energy beams transmit integrated circuit images, patterns, or photomasks (or masks or reticles) to photosensitive resists on semiconductor wafer substrates, formed (or printed or transferred) as multiple layers of patterned materials overlaid on the substrate. For each patterned layer formed on the substrate, there may be one or more masks used to form the printed patterns on the wafer. The patterns are typically expressed as polygons on the masks. However, due to a variety of optical effects, the polygons of the mask transferred to or imaged on the wafer will be smoothed and distorted during the lithographic process of transferring the mask patterns to the wafer because of a variety of optical effects. Design rules, also referred to as ground rules, establish geometric constraints or recommendations on the physical layout of an IC. Design rule checking (DRC) is the process of determining whether the physical layout of a given IC satisfies the corresponding design rules. The design rules reflect the risk of manufacturing a failed device, and passing the DRC can ensure a higher yield.